The present invention generally pertains to burn-in testing of integrated circuits that are fabricated simultaneously in a wafer, and is particularly directed to an improvement in the wafer that facilitates burn-in testing of integrated circuits at the wafer level.
Burn-in testing of an integrated circuit chip is a procedure wherein the chip is operated at a predetermined temperature level over a prolonged period. Power is applied to certain contacts of the chip; and the performance of the chip during the burn-in period is measured by monitoring test signals produced at certain other contacts of the chip.
In the prior art many integrated circuits are fabricated simultaneously in a single wafer. The wafer contains an array of integrated circuit dice, with the dice being separated by scribe lanes in which the wafer is cut to dice the wafer into individual die. For functionality testing the separated individual chips are tested individually. However, for burn-in testing one practice has been to assemble a plurality of the separated individual integrated circuit chips that have passed functionality testing into a single functional module. Modules that pass burn-in testing eventually are assembled into products. Another prior-art burn-in testing practice has been to burn in an individual single integrated circuit die that has been packaged with pins by using a burn-in board having sockets for receiving the pins.
Whenever a single integrated circuit chip of the module fails the burn-in test, the entire module may be discarded if the module is unrepairable in view of ultrafine surface features of the module and dense packing of the chips into the modules. Thus the failure of a single chip during the burn-in test results in a discard-cost factor that is several times the cost of a single chip. For example, when a multi-chip module substrate with a bare, tested cost of $200.00 is assembled with ten chips having an average cost of $50.00 each, and the assembly and burn-in-test for a completed module costs are typically $100.00, the failure of a single $50.00 chip results in scrapping an $800.00 module.